View R1LV0416C-I_1014577.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

R1LV0416C-I Series
Wide Temperature Range Version 4M SRAM (256-kword x 16-bit)
REJ03C0105-0200Z Rev. 2.00 May.26.2004
Description
The R1LV0416C-I is a 4-Mbit static RAM organized 256-kword x 16-bit. R1LV0416C-I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). The R1LV0416C-I Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has packaged in 44-pin TSOP II.
Features
* Single 2.5 V and 3.0 V supply: 2.2 V to 3.6 V * Fast access time: 55/70 ns (max) * Power dissipation: Active: 5.0 mW/MHz (typ)(VCC = 2.5 V) : 6.0 mW/MHz (typ) (VCC = 3.0 V) Standby: 1.25 W (typ) (VCC = 2.5 V) : 1.5 W (typ) (VCC = 3.0 V) * Completely static memory. No clock or timing strobe required * Equal access and cycle times * Common data input and output. Three state output * Battery backup operation. 2 chip selection for battery backup * Temperature range: -40 to +85C
Rev.2.00, May.26.2004, page 1 of 16
R1LV0416C-I Series
Ordering Information
Type No. R1LV0416CSB-5SI R1LV0416CSB-7LI Access time 55 ns 70 ns Package 400-mil 44-pin plastic TSOP II (44P3W-H)
Rev.2.00, May.26.2004, page 2 of 16
R1LV0416C-I Series
Pin Arrangement
44-pin TSOP A4 A3 A2 A1 A0 CS1# I/O0 I/O1 I/O2 I/O3 V CC V SS I/O4 I/O5 I/O6 I/O7 WE# A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (Top view) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE# UB# LB# I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 CS2 A8 A9 A10 A11 A12
Pin Description
Pin name A0 to A17 I/O0 to I/O15 CS1# (CS1) CS2 OE# (OE) WE# (WE) LB# (LB) UB# (UB) VCC VSS Function Address input Data input/output Chip select 1 Chip select 2 Output enable Write enable Lower byte select Upper byte select Power supply Ground
Rev.2.00, May.26.2004, page 3 of 16
R1LV0416C-I Series
Block Diagram
LSB V CC V SS
* * * * *
A12 A11 A10 A9 A8 A13 Row decoder
A14 A15 A16 A17 MSB A7
Memory matrix 2,048 x 2,048
I/O0 Input data control I/O15
* *
Column I/O Column decoder
* *
LSB A4 A3 A2 A1 A5 A6 A0 MSB
* *
CS2 CS1# LB# UB# WE# OE#
Control logic
Rev.2.00, May.26.2004, page 4 of 16
R1LV0416C-I Series
Operation Table
CS1# CS2 H x x L L L L L L L x L x H H H H H H H WE# x x x H H H L L L H OE# x x x L L L x x x H UB# x x H L H L L H L x LB# x x H L L H L L H x I/O0 to I/O7 High-Z High-Z High-Z Dout Dout High-Z Din Din High-Z High-Z I/O8 to I/O15 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z Operation Standby Standby Standby Read Lower byte read Upper byte read Write Lower byte write Upper byte write Output disable
Note: H: VIH, L: VIL, x: VIH or VIL
Absolute Maximum Ratings
Parameter Power supply voltage relative to VSS Terminal voltage on any pin relative to VSS Power dissipation Operating temperature Storage temperature range Storage temperature range under bias Symbol VCC VT PT Topr Tstg Tbias Value -0.5 to +4.6 -0.5*1 to VCC + 0.3*2 0.7 -40 to +85 -65 to +150 -40 to +85 Unit V V W C C C
Notes: 1. VT min: -3.0 V for pulse half-width 30 ns. 2. Maximum voltage is +4.6 V.
DC Operating Conditions
(Ta = -40 to +85C)
Parameter Supply voltage Symbol VCC VSS Input high voltage VCC = 2.2 V to 2.7 V VIH VCC = 2.7 V to 3.6 V VIH Input low voltage Note: VCC = 2.2 V to 2.7 V VIL VCC = 2.7 V to 3.6 V VIL Min 2.2 0 2.0 2.2 -0.2 -0.3 Typ 2.5/3.0 0 Max 3.6 0 Unit V V Note
VCC + 0.3 V VCC + 0.3 V 0.4 0.6 V V 1 1
1. VIL min: -3.0 V for pulse half-width 30 ns.
Rev.2.00, May.26.2004, page 5 of 16
R1LV0416C-I Series
DC Characteristics
Parameter Input leakage current Output leakage current Symbol Min |ILI| |ILO| Typ Max Unit Test conditions 1 1 A A Vin = VSS to VCC CS1# = VIH or CS2 = VIL or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC CS1# = VIL, CS2 = VIH, Others = VIH/VIL, II/O = 0 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL Cycle time = 1 s, duty = 100%, II/O = 0 mA, CS1# 0.2 V, CS2 VCC - 0.2 V VIH VCC - 0.2 V, VIL 0.2 V CS2 = VIL Vin 0 V (1) 0 V CS2 0.2 V or (2) CS1# VCC - 0.2 V, CS2 VCC - 0.2 V or (3) LB# = UB# VCC - 0.2 V, CS2 VCC - 0.2 V, CS1# 0.2 V IOH = -0.5 mA IOH = -1 mA IOH = -100 A IOL = 0.5 mA IOL = 2 mA IOL = 100 A
Operating current Average operating current
ICC ICC1

5*1 8*1
20 25
mA mA
ICC2
2*1
5
mA
Standby current Standby current -5SI to +85C to +70C to +40C to +25C -7LI to +85C to +70C to +40C to +25C Output high voltage
ISB ISB1 ISB1 ISB1 ISB1 ISB1 ISB1 ISB1 ISB1
2.0 2.4
0.1*1 0.3 0.7* 0.5* 0.7* 0.5* -- --
2 1 2 1
mA A A A A A A A A V V V V V V
10 8 3 3 20 16 10 10 -- -- -- 0.4 0.4 0.2
VCC =2.2 V to 2.7 V VOH VCC =2.7 V to 3.6 V VOH VCC =2.2 V to 3.6 V VOH2
VCC - 0.2 -- -- -- -- -- -- --
Output low voltage VCC =2.2 V to 2.7 V VOL VCC =2.7 V to 3.6 V VOL VCC =2.2 V to 3.6 V VOL2
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and specified loading, and not guaranteed. 2. Typical values are at VCC = 3.0 V, Ta = +40C and specified loading, and not guaranteed.
Rev.2.00, May.26.2004, page 6 of 16
R1LV0416C-I Series
Capacitance
(Ta = +25C, f = 1.0 MHz)
Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min Typ Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1
1. This parameter is sampled and not 100% tested.
AC Characteristics
(Ta = -40 to +85C, VCC = 2.2 V to 3.6 V, unless otherwise noted.) Test Conditions * Input pulse levels: VIL = 0.4 V, VIH = 2.2 V (VCC = 2.2 V to 2.7 V) : VIL = 0.4 V, VIH = 2.4 V (VCC = 2.7 V to 3.6 V) * Input rise and fall time: 5 ns * Input/output timing reference levels: 1.1 V (VCC = 2.2 V to 2.7 V) : 1.4 V (VCC = 2.7 V to 3.6 V) * Output load: See figures (Including scope and jig)
VTM 1.4 V
R1 Dout R1 = 3070 30pF R2 R2 = 3150 VTM = 2.3 V Dout 50pF
RL=500
Output load (A) (VCC = 2.2 V to 2.7 V)
Output load (B) (VCC = 2.7 V to 3.6 V)
Rev.2.00, May.26.2004, page 7 of 16
R1LV0416C-I Series Read Cycle
R1LV0416C-I -5SI Parameter Read cycle time Address access time Chip select access time Symbol tRC tAA tACS1 tACS2 Output enable to output valid Output hold from address change LB#, UB# access time Chip select to output in low-Z tOE tOH tBA tCLZ1 tCLZ2 LB#, UB# disable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z tBLZ tOLZ tCHZ1 tCHZ2 LB#, UB# disable to high-Z Output disable to output in high-Z tBHZ tOHZ Min 55 10 10 10 5 5 0 0 0 0 Max 55 55 55 35 55 20 20 20 20 -7LI Min 70 10 10 10 5 5 0 0 0 0 Max 70 70 70 40 70 25 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes
Rev.2.00, May.26.2004, page 8 of 16
R1LV0416C-I Series Write Cycle
R1LV0416C-I -5SI Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width LB#, UB# valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Write to output in high-Z Symbol tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ Min 55 50 50 40 50 0 0 25 0 5 0 0 Max 20 20 -7LI Min 70 60 60 50 55 0 0 30 0 5 0 0 Max 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2 1, 2, 3 1, 2 6 7 5 4 Notes
Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occures during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
Rev.2.00, May.26.2004, page 9 of 16
R1LV0416C-I Series
Timing Waveform
Read Timing Waveform (WE# = VIH)
t RC Address tAA tACS1 CS1# tCLZ1*2, 3 tCHZ1 1, 2, 3 * Valid address
CS2
tACS2 tCLZ2*2, 3 tCHZ2*1, 2, 3 tBHZ*1, 2, 3 tBA
LB#, UB# tBLZ*2, 3 tOE OE# tOLZ*2, 3 Dout High impedance Valid data tOH tOHZ*1, 2, 3
Rev.2.00, May.26.2004, page 10 of 16
R1LV0416C-I Series Write Timing Waveform (1) (WE# Clock)
tWC Address Valid address tWR*7
tCW*5 CS1# tCW*5 CS2 tBW LB#, UB# tAW tWP*4 WE# tAS*6 tDW Din tWHZ*1, 2 Valid data
tDH
tOW*2 High impedance
Dout
Rev.2.00, May.26.2004, page 11 of 16
R1LV0416C-I Series Write Timing Waveform (2) (CS# Clock, OE# = VIH)
tWC Address Valid address tAW tAS CS1# tCW*5 CS2 tBW LB#, UB# *6 tCW*5 tWR*7
tWP*4 WE# tDW Din Valid data tDH
High impedance Dout
Rev.2.00, May.26.2004, page 12 of 16
R1LV0416C-I Series Write Timing Waveform (3) (LB#, UB# Clock, OE# = VIH)
tWC Address Valid address tAW tCW*5 CS1# tCW*5 CS2 tAS*6 LB#, UB# tBW tWR*7
tWP*4 WE# tDW Din Valid data tDH
High impedance Dout
Rev.2.00, May.26.2004, page 13 of 16
R1LV0416C-I Series
Low VCC Data Retention Characteristics
(Ta = -40 to +85C)
Parameter VCC for data retention Symbol Min Typ VDR 2.0 Max Unit Test conditions*3 V Vin 0V (1) 0 V CS2 0.2 V or (2) CS2 VCC - 0.2 V, CS1# VCC - 0.2 V or (3) LB# = UB# VCC - 0.2 V, CS2 VCC - 0.2 V, CS1# 0.2 V VCC = 3.0 V, Vin 0V (1) 0 V CS2 0.2 V or (2) CS2 VCC - 0.2 V, CS1# VCC - 0.2 V or (3) LB# = UB# VCC - 0.2 V, CS2 VCC - 0.2 V, CS1# 0.2 V
Data retention current
-5SI
to +85C to +70C to +40C to +25C
ICCDR ICCDR ICCDR ICCDR ICCDR ICCDR ICCDR ICCDR tCDR tR
0
0.5* 0.7* 0.5*
2 1 1
10 8
A A A A A A A A ns ns
0.7*2 3 3 20 16 10 10
-7LI
to +85C to +70C to +40C to +25C
Chip deselect to data retention time Operation recovery time
See retention waveform
tRC*4
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and specified loading, and not guaranteed. 2. Typical values are at VCC = 3.0 V, Ta = +40C and specified loading, and not guaranteed. 3. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#, I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 VCC - 0.2 V or 0 V CS2 0.2 V. The other input levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high impedance state. 4. tRC = read cycle time.
Rev.2.00, May.26.2004, page 14 of 16
R1LV0416C-I Series Low VCC Data Retention Timing Waveform (1) (CS1# Controlled) (VCC = 2.2 V to 2.7 V)
t CDR V CC 2.2 V Data retention mode tR
V DR 2.0 V CS1# 0V CS1# VCC - 0.2 V
Low VCC Data Retention Timing Waveform (2) (CS1# Controlled) (VCC = 2.7 V to 3.6 V)
t CDR V CC 2.7 V Data retention mode tR
2.2 V V DR CS1# 0V CS1# VCC - 0.2 V
Low VCC Data Retention Timing Waveform (3) (CS2 Controlled) (VCC = 2.2 V to 2.7 V)
t CDR V CC 2.2 V CS2 V DR 0.4 V 0V 0 V < CS2 < 0.2 V Data retention mode tR
Rev.2.00, May.26.2004, page 15 of 16
R1LV0416C-I Series Low VCC Data Retention Timing Waveform (4) (CS2 Controlled) (VCC = 2.7 V to 3.6 V)
t CDR V CC 2.7 V CS2 V DR 0.6 V 0V 0 V < CS2 < 0.2 V Data retention mode tR
Low VCC Data Retention Timing Waveform (5) (LB#, UB# Controlled) (VCC = 2.2 V to 2.7 V)
t CDR V CC 2.2 V Data retention mode tR
V DR 2.0 V LB#, UB# 0V LB#, UB# VCC - 0.2 V
Low VCC Data Retention Timing Waveform (6) (LB#, UB# Controlled) (VCC = 2.7 V to 3.6 V)
t CDR V CC 2.7 V Data retention mode tR
2.2 V V DR LB#, UB# 0V LB#, UB# VCC - 0.2 V
Rev.2.00, May.26.2004, page 16 of 16
Revision History
Rev. Date
R1LV0416C-I Series Data Sheet
Contents of Modification Page Description Initial issue Absolute Maximum Ratings Notes 2 : +7.0 V to +4.6 V DC characteristics -5SI and -7LI items' description are divided. AC characteristics Read Cycle/Notes: tCLZ1/tCLZ2/tBLZ/tOLZ : Addition of [2, 3] tCHZ1/tCHZ2/tBHZ/tOHZ : Addition of [1, 2, 3] Write Cycle/Notes: tOHZ : Addition of [1, 2, 3] Low VCC Data Retention Characteristics -5SI and -7LI items' description are divided. 5 6 7 8
1.00 2.00
Aug.05.2003 May.26.2004
9 14
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c) 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .1.0

▲Up To Search▲

Price & Availability of R1LV0416C-I

	To Download R1LV0416C-I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .